Low-power VLSI decoder architectures for LDPC codes
Proceedings of the 2002 international symposium on Low power electronics and design
Partially-Parallel LDPC Decoder Based on High-Efficiency Message-Passing Algorithm
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Good error-correcting codes based on very sparse matrices
IEEE Transactions on Information Theory
Design of capacity-approaching irregular low-density parity-check codes
IEEE Transactions on Information Theory
Analysis of sum-product decoding of low-density parity-check codes using a Gaussian approximation
IEEE Transactions on Information Theory
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A partially-parallel decoder architecture for irregular LDPC code targeting high throughput and low cost applications is proposed. The design is based on a novel sum-delta message passing algorithm that facilitates the decoding throughput by removing redundant computations and decreases the hardware cost by optimizing the storage. Techniques such as binary sorting, parallel column operation, high performance pipelining are used to further speed up the message passing procedure. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5X improvement in throughput, which reaches 402 Mbps at the frequency of 200MHz, with 11% area reduction.