Performance comparison of DSP and VHDL implementation of trellis coded demodulation

  • Authors:

  • Amit S. Awati;Hrishikesh R. Kanitkar;Mahima Nanda;Nikil G. Laddha;Savit G. Kulkarni;Anuradha C. Phadke;Alwind D. Anuse

  • Affiliations:

  • Electronics and Telecommunication Department, Pune University, Maharashtra Institute of Technology, Kothrud, Pune, India;Electronics and Telecommunication Department, Pune University, Maharashtra Institute of Technology, Kothrud, Pune, India;Electronics and Telecommunication Department, Pune University, Maharashtra Institute of Technology, Kothrud, Pune, India;Electronics and Telecommunication Department, Pune University, Maharashtra Institute of Technology, Kothrud, Pune, India;Electronics and Telecommunication Department, Pune University, Maharashtra Institute of Technology, Kothrud, Pune, India;Electronics and Telecommunication Department, Pune University, Maharashtra Institute of Technology, Kothrud, Pune, India;Electronics and Telecommunication Department, Pune University, Maharashtra Institute of Technology, Kothrud, Pune, India

  • Venue:
  • ESPOCO'05 Proceedings of the 4th WSEAS International Conference on Electronic, Signal Processing and Control
  • Year:
  • 2007

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Abstract

In most wireless communication systems, convolutional coding is the preferred method of error correction coding to overcome transmission distortions. In this paper we have compared the performance of trellis coded demodulator (viterbi decoder) implemented on TMS320C54XX DSP chip and FPGA Spartan II XC2s50PQ208 kit. In this paper we also present a modified viterbi algorithm in which we have completely eliminated register exchange and traceback approach i.e. no retracing of the survivor path is required which thereby reduces memory requirement, power consumption and reduces the time required for getting the decoded output.