VHDL generation from SDL specifications
CHDL'97 Proceedings of the IFIP TC10 WG10.5 international conference on Hardware description languages and their applications : specification, modelling, verification and synthesis of microelectronic systems: specification, modelling, verification and synthesis of microelectronic systems
An Evolutionary Approach to Automatic Generation of VHDL Code for Low-Power Digital Filters
EuroGP '01 Proceedings of the 4th European Conference on Genetic Programming
RSP '96 Proceedings of the 7th IEEE International Workshop on Rapid System Prototyping (RSP '96)
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Documentation of a complex design is essential for the reuse and for the verification. Spreadsheet applications, such as MS-Excel, are often used to design and document certain parts of system-on-chip designs. For example interrupt and DMA connections are easy to describe in a table format. To facilitate the implementation, the actual HDL code can be automatically generated from the spreadsheet documentation. The benefit of this approach is that the HDL implementation is always in tact with the documentation and vice versa. The quality of design and documentation is also usually better when the manual coding is not needed. In addition, h-files and compilation scripts needed later in the flow can be generated along with the HDL code, which facilitates the use of the design. This paper presents an approach and a tool to generate VHDL code and h-files from MS-Excel spreadsheet. The approach is presented with two examples: interrupt and DMA connections. The results show that the method dramatically reduces the time needed to the subsystem implementation.