FPGA based data coding

Authors:
Ali M. Al-Haj
Affiliations:
Department of Computer Engineering, College of Electrical Engineering, Princess Sumaya University for Technology, Amman, Jordan
Venue:
ISPRA'05 Proceedings of the 4th WSEAS International Conference on Signal Processing, Robotics and Automation
Year:
2005

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Abstract

In this paper, we describe an efficient high-speed implementation of the well-known arithmetic coding algorithm. The implementation is based on mapping the multiply-intensive computation of the arithmetic coding algorithm, on the embedded-multiplier rich, Xilinx Virtex FPGAs. The reported configurable hardware implementation accelerates the execution speed of the arithmetic coding algorithm, thus facilitating a wider usage of the algorithm in real-time coding applications such as audio and video compression.