A scalable LDPC decoder ASIC architecture with bit-serial message exchange

  • Authors:

  • Tyler Brandon;Robert Hang;Gary Block;Vincent C. Gaudet;Bruce Cockburn;Sheryl Howard;Christian Giasson;Keith Boyle;Paul Goud;Siavash Sheikh Zeinoddin;Anthony Rapley;Stephen Bates;Duncan Elliott;Christian Schlegel

  • Affiliations:

  • Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada T6G 2V4;Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada T6G 2V4;Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada T6G 2V4;Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada T6G 2V4;Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada T6G 2V4;Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada T6G 2V4;Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada T6G 2V4;Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada T6G 2V4;Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada T6G 2V4;Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada T6G 2V4;Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada T6G 2V4;Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada T6G 2V4;Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada T6G 2V4;Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada T6G 2V4

  • Venue:
  • Integration, the VLSI Journal
  • Year:
  • 2008

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Abstract

We present a scalable bit-serial architecture for ASIC realizations of low-density parity check (LDPC) decoders. Supporting the architecture's potential, we describe a decoder implementation for a (256,128) regular-(3,6) LDPC code that has a decoded information throughput of 250Mbps, a core area of 6.96mm^2 in 180-nm 6-metal CMOS, and an energy efficiency of 7.56nJ per uncoded bit at low signal-to-noise ratios. The decoder is fully block-parallel, with all bits of each 256-bit codeword being processed by 256 variable nodes and 128 parity check nodes that together form an 8-stage iteration pipeline. Extrinsic messages are exchanged bit-serially between the variable and parity check nodes to significantly reduce the interleaver wiring. Parity check node processing is also bit-serial. The silicon implementation performs 32 iterations of the min-sum decoding algorithm on two staggered codewords in the same pipeline. The results of a supplementary layout study show that the reduced wiring congestion makes the decoder readily scaleable up to the longer kilobit-size LDPC codewords that appear in important emerging communication standards.