High-speed codebook design by the multipath competitive learning on a systolic memory architecture

Authors:
Kentaro Sano;Chiaki Takagi;Kenichi Suzuki;Tadao Nakamura
Affiliations:
Graduate School of Information Sciences, Tohoku University, Sendai, Japan;Graduate School of Information Sciences, Tohoku University, Sendai, Japan;Graduate School of Information Sciences, Tohoku University, Sendai, Japan;Graduate School of Information Sciences, Tohoku University, Sendai, Japan
Venue:
ISCGAV'04 Proceedings of the 4th WSEAS International Conference on Signal Processing, Computational Geometry & Artificial Vision
Year:
2004

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Abstract

So far, we have proposed a dedicated processor based on a systolic memory architecture to accelerate competitive learning (CL) for optimal codebook design. While this processor achieves high-speed codebook design, it has essential problems: limitation of hardware resources and lack in flexibility of codebook size. To solve these problems, we present a multipath CL algorithm that allows the processor to flexibly handle the various size of a codebook. The multipath CL on the FPGA-based prototype of the processor could design codebooks with comparable MSEs to the software simulation while the prototype processor achieved 2000 times faster processing speed than a general-purpose processor.