A freespace crossbar for multi-core processors

  • Authors:
  • Michel N. Victor;Aris K. Silzars;Edward S. Davidson

  • Affiliations:
  • Exaconnect, Sunnyside, NY, USA;Exaconnect, Sammamish, WA, USA;University of Michigan, Ann Arbor, MI, USA

  • Venue:
  • Proceedings of the 22nd annual international conference on Supercomputing
  • Year:
  • 2008

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Abstract

A new package-level interconnect is described that adapts carbon nanoemissive display technology to create an inexpensive package-level freespace crossbar with single-cycle source-to-target latency. Interconnections are made using filamentary electron beams as the data transmission medium. The beams are electrostatically steered, enabling very large, low latency inter-chip crossbar networks. The crossbar and associated package are built entirely from existing technology. This paper describes the operation of the crossbar and presents a conceptual design for a processor that uses the crossbar.