Hardware/software partitioning and simulation with SystemC

Authors:
Richard Gallery;Deepesh M. Shakya
Affiliations:
School of Informatics & Engineering, Institute of Technology, Blanchardstown, Dublin, Ireland;School of Informatics & Engineering, Institute of Technology, Blanchardstown, Dublin, Ireland
Venue:
ICECS'03 Proceedings of the 2nd WSEAS International Conference on Electronics, Control and Signal Processing
Year:
2003

Citing 5
Cited 0

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Abstract

This paper gives an overview of how the speed of simulation of Video/Graphics subsystem can be increased with SystemC [1][5][6]. Also, an idea of partitioning hardware and software at instruction level and the simulation framework to support this partitioning has been introduced. The simulation of each design space is conducted at the transaction level and the partitioning decision, which is effectively a selection of suitable design space, is made on the basis of the number of instructions, resource wastage factor and the hardware cost involved in the design space.