Lattice basis reduction: improved practical algorithms and solving subset sum problems
Mathematical Programming: Series A and B
A course in computational algebraic number theory
A course in computational algebraic number theory
A decade of reconfigurable computing: a visionary retrospective
Proceedings of the conference on Design, automation and test in Europe
On Limits of Wireless Communications in a Fading Environment when UsingMultiple Antennas
Wireless Personal Communications: An International Journal
Seamless Hardware-Software Integration in Reconfigurable Computing Systems
IEEE Design & Test
Automatic Design of Area-Efficient Configurable ASIC Cores
IEEE Transactions on Computers
Introduction to Space-Time Wireless Communications
Introduction to Space-Time Wireless Communications
A universal lattice code decoder for fading channels
IEEE Transactions on Information Theory
Closest point search in lattices
IEEE Transactions on Information Theory
On maximum-likelihood detection and the search for the closest lattice point
IEEE Transactions on Information Theory
From theory to practice: an overview of MIMO space-time coded wireless systems
IEEE Journal on Selected Areas in Communications
Prototype experience for MIMO BLAST over third-generation wireless system
IEEE Journal on Selected Areas in Communications
Array like runtime reconfigurable MIMO detectors for 802.11n WLAN: a design case study
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
FPGA design of box-constrained MIMO detector
ICC'09 Proceedings of the 2009 IEEE international conference on Communications
Reconfigurable real-time MIMO detector on GPU
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
Systolic like soft-detection architecture for 4x4 64-QAM MIMO system
Proceedings of the Conference on Design, Automation and Test in Europe
A radius adaptive K-Best decoder with early termination: algorithm and VLSI architecture
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2009 IEEE custom integrated circuits conference
A pipeline interleaved heterogeneous SIMD soft processor array architecture for MIMO-OFDM detection
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
Efficient Ordering Schemes for High-Throughput MIMO Detectors
Journal of Signal Processing Systems
Implementation of a High Throughput Soft MIMO Detector on GPU
Journal of Signal Processing Systems
High-throughput soft-output MIMO detector based on path-preserving trellis-search algorithm
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Self-Reconfigurable Constant Multiplier for FPGA
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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Multiple-input-multiple-output (MIMO) systems use multiple antennas in both transmitter and receiver ends for higher spectrum efficiency. The hardware implementation of MIMO detection becomes a challenging task as the computational complexity increases. This paper presents the architectures and implementations of two typical sphere decoding algorithms, including the Viterbo-Boutros (VB) algorithm and the Schnorr-Euchner (SE) algorithm. Hardware/software codesign technique is applied to partition the decoding algorithm on a single field-programmable gate array (FPGA) device. Three levels of parallelism are explored to improve the decoding rate: the concurrent execution of the channel matrix preprocessing on an embedded processor and the decoding functions on customized hardware modules, the parallel decoding of real/imaginary parts for complex constellation, and the concurrent execution of multiple steps during the closest lattice point search. The decoders for a 4 × 4 MIMO system with 16-QAM modulation are prototyped on a Xilinx XC2VP30 FPGA device with a MicroBlaze soft core processor. The hardware prototypes of the SE and VB algorithms show that they support up to 81.5 and 36.1 Mb/s data rates at 20 dB signal-to-noise ratio, which are about 22 and 97 times faster than their respective implementations in a digital signal processor.