An FPGA-based implementation of the Pomaranch stream cipher

Authors:
Paris Kitsos;Odysseas Koufopavlou
Affiliations:
Hellenic Open University (HOU), Tsamadou, Patras, GR, Greece;University of Patras, Rio, GR, Greece
Venue:
Proceedings of the 3rd international conference on Mobile multimedia communications
Year:
2007

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Abstract

As the versatility of small, low power devices increases and their use becomes commonplace, a need for secure communications among these devices has arisen. Pomaranch is a recently developed stream cipher with two major advantages: (i) the low hardware complexity, which results in small area and (ii) the good statistical properties. This architecture supports an 80-bit key and 32- to 108-bit IV. FPGA devices were used for the performance demonstration. A maximum throughput equal to 279 Mbps can be achieved, with a clock frequency of 279 MHz.