On Limits of Wireless Communications in a Fading Environment when UsingMultiple Antennas
Wireless Personal Communications: An International Journal
An efficient square-root algorithm for BLAST
ICASSP '00 Proceedings of the Acoustics, Speech, and Signal Processing, 2000. on IEEE International Conference - Volume 02
FPGA design of box-constrained MIMO detector
ICC'09 Proceedings of the 2009 IEEE international conference on Communications
FPGA prototyping of a high data rate LTE uplink baseband receiver
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
MIMO accelerator: a design flow for a programmable MIMO decoder architecture
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
A MIMO decoder accelerator for next generation wireless communications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Implementation of a High-Speed MIMO Soft-Output Symbol Detector for Software Defined Radio
Journal of Signal Processing Systems
Numerical Aspects of MIMO OFDM PHY Layer Applications on SDR Platforms
Journal of Signal Processing Systems
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Design and implementation of a highly optimized MIMO (multiple-input multiple-output) detector requires cooptimization of the algorithm with the underlying hardware architecture. Special attention must be paid to application requirements such as throughput, latency, and resource constraints. In this work, we focus on a highly optimized matrix inversion free 4 × 4 MMSE (minimum mean square error) MIMO detector implementation. The work has resulted in a real-time field-programmable gate array-based implementation (FPGA-) on a Xilinx Virtex-2 6000 using only 9003 logic slices, 66 multipliers, and 24 Block RAMs (less than 33% of the overall resources of this part). The design delivers over 420 Mbps sustained throughput with a small 2.77-microsecond latency. The designed 4 × 4 linear MMSE MIMO detector is capable of complying with the proposed IEEE 802.11n standard.