On threshold circuits for parity

  • Authors:
  • R. Paturi;M. E. Saks

  • Affiliations:
  • Dept. of Comput. Sci.&Eng., California Univ., San Diego, La Jolla, CA, USA;Dept. of Comput. Sci.&Eng., California Univ., San Diego, La Jolla, CA, USA

  • Venue:
  • SFCS '90 Proceedings of the 31st Annual Symposium on Foundations of Computer Science
  • Year:
  • 1990

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Abstract

Motivated by, the problem of understanding the limitations of neural networks for representing Boolean functions, the authors consider size-depth tradeoffs for threshold circuits that compute the parity function. They give an almost optimal lower bound on the number of edges of any depth-2 threshold circuit that computes the parity function with polynomially bounded weights. The main technique used in the proof, which is based on the theory of rational approximation, appears to be a potentially useful technique for the analysis of such networks. It is conjectured that there are no linear size, bounded-depth threshold circuits for computing parity.