Asynchronous PRAMs are (almost) as good as synchronous PRAMs

Authors:
C. Martel;R. Subramonian;A. Part
Affiliations:
Div. of Comput. Sci., California Univ., Davis, CA, USA;Div. of Comput. Sci., California Univ., Davis, CA, USA;Div. of Comput. Sci., California Univ., Davis, CA, USA
Venue:
SFCS '90 Proceedings of the 31st Annual Symposium on Foundations of Computer Science
Year:
1990

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Writing-all deterministically and optimally using a nontrivial number of asynchronous processors

ACM Transactions on Algorithms (TALG)

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Abstract

A PRAM (parallel random-access-machine) model that allows processors to have arbitrary asynchronous behavior is introduced. The main result shows that any n-processor CRCW (concurrent-read, concurrent-write) PRAM program can be simulated on an asynchronous CRCW PRAM using O(n) expected work per parallel step and up to n/log n log*n asynchronous processors. It is shown that a synchronization primitive for n parallel instructions can be computed using O(n) expected work by a system of asynchronous processors. Since a special case of asynchronous behavior is a fail-stop error, the simulation technique described above can convert any PRAM program into a PRAM program that is resistant to all fail-stop errors and has the same expected work as the original program.