Euro-Par '00 Proceedings from the 6th International Euro-Par Conference on Parallel Processing
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Efficient bufferless packet switching on trees and leveled networks
Journal of Parallel and Distributed Computing
A new bound for pure greedy hot potato routing
STACS'07 Proceedings of the 24th annual conference on Theoretical aspects of computer science
Deterministic hot-potato permutation routing on the mesh and the torus
TAMC'08 Proceedings of the 5th international conference on Theory and applications of models of computation
EDXY - A low cost congestion-aware routing algorithm for network-on-chips
Journal of Systems Architecture: the EUROMICRO Journal
Efficient bufferless routing on leveled networks
Euro-Par'05 Proceedings of the 11th international Euro-Par conference on Parallel Processing
WAOA'04 Proceedings of the Second international conference on Approximation and Online Algorithms
Energy-aware fault-tolerant network-on-chips for addressing multiple traffic classes
Microprocessors & Microsystems
Potential Function Analysis of Greedy Hot-Potato Routing
Theory of Computing Systems
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The authors consider a form of packet routing known as hot potato routing or deflection routing. Its striking feature is that there are no buffers at intermediate nodes. Thus packets are always moving (possibly in the 'wrong' direction), giving rise to the term 'hot potato'. They give a simple deterministic algorithm that on a n*n torus will route a random instance in 2n+O(log n) steps with high probability. They add random delays to this algorithm so that it solves the permutation routing problem on the torus in 9n steps with high probability, on every instance. On a hypercube with N=2/sup n/ nodes, they give a simple deterministic algorithm that will route a random instance in O(n) steps with high probability. Various other results are discussed.