A novel effective address calculation mechanism for RISC microprocessors
ACM SIGARCH Computer Architecture News - Special Issue: Architectural Support for Operating Systems
Multithreading with Distributed Functional Units
IEEE Transactions on Computers
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A semi-absolute branch instruction supplies the low-order bits of the destination address, or an offset into a frame, while the high-order bits the destination address, or frame number, are derived from the current frame number. The branch mechanism proposed here compares a small number of the most significant bits of a current and destination frame offsets followed by a possible increment or decrement of the current frame number, allowing branches to be effected more rapidly, for a given hardware cost, than by adding an offset to the instruction pointer. The increment can be performed upon branching or prior to it in order to hide the latency of the increment operation. If, for example, the three most significant bits of the frame offsets are compared the overall branch range is reduced to 94% of the range of conventional relative branches. This technique over comes the branch range restriction that occurs when the instruction pointer points to near a frame boundary and the destination address is generated by a simple bit-field substitution.