A subclass of Petri Nets as design abstraction for parallel architectures

Authors:
Werner B. Joerg
Affiliations:
Concurrent Systems Laboratory, Department of Electrical Engineering, Computer Engineering Division, University of Alberta, Edmonton, Alberta T6G 2G7 Canada
Venue:
ACM SIGARCH Computer Architecture News
Year:
1990

Citing 7
Cited 2

On the models for designing VLSI asynchronous digital systems

Integration, the VLSI Journal
Isomorphisms Between Petr Nets and Dataflow Graphs

IEEE Transactions on Software Engineering
Fifo nets without order deadlock

Acta Informatica
Representing first order logic-based specifications in Petri-net-like graphs

IWSSD '89 Proceedings of the 5th international workshop on Software specification and design
Petri nets and speed independent design

Communications of the ACM
Petri Net Theory and the Modeling of Systems

Petri Net Theory and the Modeling of Systems
PROTEAN: A High-Level Petri Net Tool for the Specification and Verification of Communication Protocols

IEEE Transactions on Software Engineering

A real-time systems context for the framework for information systems architecture

IBM Systems Journal
On Causality Semantics of Nets with Priorities

Fundamenta Informaticae

Quantified Score

Hi-index	0.00

Visualization

Abstract

In spite of their increasing popularity for modeling and performance analysis of parallel systems, Petri nets play only a marginal role in the area of synthesis of asynchronous hardware. It is suggested that a change in the perception of their role will lead to a cost effective design method for parallel asynchronous architectures. A hardware implementable subclass of Petri nets is presented that exploits conflicts as a nondeterministic scheduling feature and that offers token evaluation as an option for path selection. The net primitives, complemented with functional primitives, constitute the lowest abstractions for a data flow oriented design paradigm.