Definition and SIMD implementation of a multi-processing architecture approach on FPGA

Authors:
Philippe Bonnot;Fabrice Lemonnier;Gilbert Edelin;Gérard Gaillat;Olivier Ruch;Pascal Gauget
Affiliations:
Thales Research & Technology, Palaiseau, France;Thales Research & Technology, Palaiseau, France;Thales Research & Technology, Palaiseau, France;Thales Optronique SA, Guyancourt, France;Thales Optronique SA, Guyancourt, France;Thales Optronique SA, Guyancourt, France
Venue:
Proceedings of the conference on Design, automation and test in Europe
Year:
2008

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Abstract

In a context of high performance, low technology access cost and application code reusability objectives, this paper presents an "architectured FPGA" approach that consists in the definition of a general frame for embedded system application implementations. Addressing image processing as a first application domain, a FPGA architecture implementation based on that approach is presented. Built around SIMD architecture, the "Ter@Core" FPGA implementation illustrates the competitiveness of the approach compared to off-the-shelf processors and to usual FPGA approach. The presented implementation gathers 128 processing elements on a single FPGA providing 19.2 GOPS performance and very high application development productivity.