Structural synthesis of four-quadrant multiplier based on hierarchical topology

Authors:
Xiaoying Wang;Lars Hedrich
Affiliations:
University of Frankfurt, Germany;University of Frankfurt, Germany
Venue:
Proceedings of the conference on Design, automation and test in Europe
Year:
2008

Citing 2
Cited 0

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DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
RF microelectronics

RF microelectronics

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Abstract

This paper presents a method towards automatic structural synthesis of analog multiplier based on a hierarchical topology "super-topology", which is abstracted from the most standard four-quadrant multipliers. The essential components in the super-topology are four identical cells, which consist of several MOS-transistors and determine features and performances of multipliers. We build all possible cells within 3 transistors. Experimental results present three new multiplier structures with simulation results to show the creativity of our method.