IBM Systems Journal - Special issue on cryptology
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Architectural support for copy and tamper resistant software
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
Handbook of Applied Cryptography
Handbook of Applied Cryptography
An IEEE 1149.1 Based Logic/Signature Analyzer in a Chip
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
AEGIS: architecture for tamper-evident and tamper-resistant processing
ICS '03 Proceedings of the 17th annual international conference on Supercomputing
Understanding the Linux Kernel, Second Edition
Understanding the Linux Kernel, Second Edition
Hardware Engines for Bus Encryption: A Survey of Existing Techniques
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Online memory compression for embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
SecBus: operating system controlled hierarchical page-based memory bus protection
Proceedings of the Conference on Design, Automation and Test in Europe
Beyond full disk encryption: protection on security-enhanced commodity processors
ACNS'13 Proceedings of the 11th international conference on Applied Cryptography and Network Security
Memory encryption: A survey of existing techniques
ACM Computing Surveys (CSUR)
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Unencrypted data appearing on the processor-memory bus can result in security violations, e.g., allowing attackers to gather keys to financial accounts and personal data. Although on-chip bus encryption hardware can solve this problem, it requires hardware redesign or increases processor cost. Application redesign to prevent sensitive data from appearing on the processor-memory bus is extremely difficult. We propose and evaluate a processor-memory bus encryption technique for embedded systems that requires no changes to applications or hardware. This technique exploits cache locking or scratchpad memory, features present in many embedded processors, permitting the operating system (OS) virtual memory infrastructure to automatically encrypt data belonging to protected processes as they are written to off-chip memory. Pages belonging to unprotected processes are stored unencrypted to prevent performance and energy consumption penalties. We evaluate the proposed bus encryption technique using full system simulation. Experimental results indicate that it is possible to prevent the working data sets of processes from appearing on the processor-memory bus in plaintext, without using dedicated hardware and without changing applications. The OS based technique results in 1.37x slowdown for protected processes for processors with 512KB of L2 cache and 1.78x slowdown for processors with 256KB of L2 cache. There are negligible performance penalties for unprotected processes.