Exploiting multi-way branching to boost superscalar processor performance

Authors:
Yen-Jen Oyang
Affiliations:
Department of Computer Science and Information Engineering, National Taiwan University, Taipei, Taiwan
Venue:
ACM SIGPLAN Notices
Year:
1991

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Abstract

This paper discusses exploiting multi-way branching to boost superscalar processor performance. The exploitation of multi-way branching contributes to a boost in superscalar processor performance through two effects: (1) increase of instruction-level parallelism and (2) reducing of the amount of branch penalty. The work presented in this paper comprises two conjunctive parts. The first part is a compiler technique called the SV (Shadow Variable) transformation. The second part is a new multi-way branching scheme developed in conjunction with the SV transformation. The SV transformation can transform program segments which multi-way branching is originally not applicable to into ones which multi-way branching is applicable to. The proposed multi-way branching scheme, meanwhile, is able to carry out multi-way branches efficiently, especially for those derived from applying the SV transformation, and requires no expensive hardware for implementation.