On the Hardware Implementation of the 3GPP Confidentiality and Integrity Algorithms
ISC '01 Proceedings of the 4th International Conference on Information Security
Small and High-Speed Hardware Architectures for the 3GPP Standard Cipher KASUMI
ISC '02 Proceedings of the 5th International Conference on Information Security
IEEE Transactions on Consumer Electronics
Encryption System with Variable Number of Registers
Computers and Electrical Engineering
A very compact hardware implementation of the KASUMI block cipher
WISTP'10 Proceedings of the 4th IFIP WG 11.2 international conference on Information Security Theory and Practices: security and Privacy of Pervasive Systems and Smart Devices
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Modern cellular networks allow users to transmit information at high data rates, have access to IP-based networks deployed around the world, and access to sophisticated services. In this context, not only is it necessary to develop new radio interface technologies and improve existing core networks to reach success, but guaranteeing confidentiality and integrity during transmission is a must. The KASUMI block cipher lies at the core of both the f8 data confidentiality algorithm and the f9 data integrity algorithm for Universal Mobile Telecommunications System networks. KASUMI implementations must reach high performance and have low power consumption in order to be adequate for network components. This paper describes a specialized processor core designed to efficiently perform the KASUMI algorithm. Experimental results show two orders of magnitude performance improvement over software only based implementations. We describe the used design technique that can also be applied to implement other Feistel-like ciphering algorithms. The proposed architecture was implemented on a FPGA, results are presented and discussed.