The SPARC architecture manual (version 9)
The SPARC architecture manual (version 9)
The Jalapeño dynamic optimizing compiler for Java
JAVA '99 Proceedings of the ACM 1999 conference on Java Grande
Linear scan register allocation
ACM Transactions on Programming Languages and Systems (TOPLAS)
Java bytecode compression for low-end embedded systems
ACM Transactions on Programming Languages and Systems (TOPLAS)
Improving Java performance using hardware translation
ICS '01 Proceedings of the 15th international conference on Supercomputing
Java Virtual Machine Specification
Java Virtual Machine Specification
Characterization of Java Applications at Bytecode and Ultra-SPARC Machine Code Levels
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Java client ahead-of-time compiler for embedded systems
Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Revisiting Java Bytecode Compression for Embedded and Mobile Computing Environments
IEEE Transactions on Software Engineering
A simplified java bytecode compilation system for resource-constrained embedded processors
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Register allocation via coloring
Computer Languages
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Hardware bytecode translation is a technique to improve the performance of the Java virtual machine (JVM), especially on the portable devices for which the overhead of dynamic compilation is significant. However, since the translation is done on a single bytecode basis, a naive implementation of the JVM generates frequent memory accesses for local variables which can be not only a performance bottleneck but also an obstacle for instruction folding. A solution to this problem is to add a small register file to the data path of the microprocessor which is dedicated for storing local variables. However, the effectiveness of such a local variable register file depends on the size and the local variable access behavior of the applications. In this paper, we analyze the local variable access behavior of various Java applications. In particular, we will investigate the fraction of local variable accesses that are covered by the register file of a varying size, which determines the chip area overhead and the operation speed. We also evaluate the effectiveness of the sliding register window for parameter passing in context of JVM and on-the-fly optimization of local variable to register file mapping. With two types of exceptions, a 16-entry register file achieves coverages of up to 98%. The first type of exception is represented by the SAXON XSLT processor for which the effect of cold miss is significant. Adding the sliding window feature to the register file for parameter passing turns 6.2-13.3% of total accesses from miss to hit to the register file for the SAXON with XSLTMark. The second type of exception is represented by the FFT, which accesses more than 16 local variables for most of method invocations. In this case, on-the-fly profiling is effective. The hit ratio of a 16-entry register file for the FFT is increased from 44% to 83% by an array of 8-bit counters.