CAD dependent estimation of optimal k-value in FSM onto k-LUT FPGA mappings, based on standard benchmark networks

Authors:
Dokouzyannis Stavros;Arzoumanidis Efsevios
Affiliations:
Aristotle University of Thessaloniki, Department of Electrical and Computer Engineering, Thessaloniki, Greece;Aristotle University of Thessaloniki, Department of Electrical and Computer Engineering, Thessaloniki, Greece
Venue:
EHAC'08 Proceedings of the 7th WSEAS International Conference on Electronics, Hardware, Wireless and Optical Communications
Year:
2008

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Abstract

The problem of k value is a crucial one for k-LUT based FPGA architectures. A digital circuit quality mapping onto a k- LUT FPGA, is basically CAD dependable, but to a great degree k value dominates over all of the mapping parameters. Namely area and level of a mapped circuit (network) are strongly dependent on k value. As k increases, the total area of a mapped circuit also increases, while the relative level decreases, leading to a faster circuit. The question is which is the optimum k value, namely the value beyond which the area tradeoff of a mapped circuit (network) is unnecessarily increased for some level gain. This problem has been extensively studied through years and resulted in architectures implemented by most FPGAs manufacturers. For years, optimum values of k are considered between 3 and 5, with k = 4 accepted as being the best choice. Our study is an experimental evaluation of above results in present times, utilizing SIS, MVSIS and ABC, academic CAD systems, from California Berkeley University (UCB). These CAD systems, especially MVSIS and the under development ABC, incorporate state of the art optimization and mapping algorithms, among many other features. We optimized and mapped 20 medium and large scale sequential benchmark networks, for k values from 2 to 6, using all three mentioned CAD systems. In all cases our outcomes verify that k should be again in the range of 3 to 5 for best results, with k=4 being the optimum value.