Field-programmable gate arrays
Field-programmable gate arrays
Combinational logic synthesis for LUT based field programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fast place and route approaches for fpgas
Fast place and route approaches for fpgas
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As digital circuits become bigger and faster the need for effective optimization packages become crucial. SIS, an academic optimization CAD package for digital circuits, which appeared in early 90's, is unique and thus remains the basic reference regarding the performance of successor systems. Besides, SIS is unique for optimization of sequential circuits and thus valuable, regardless of its drawbacks. MVSIS is a relative new package, developed also at Berkeley University, which incorporates new ideas and algorithms, regarding optimization, and has the powerful ability to manipulate multi-valued logic networks. As a matter of fact, it is considerably faster than SIS, especially for large circuits, giving however overall comparable results for area and level. ABC, is the newest, still under development CAD package from the same university, appears to have a challenging performance for large circuits; especially regarding the time needed for optimization. In this paper we try to compare the performance of the mentioned CAD software systems using three criteria. Namely, the time needed to get best optimization results, the area and the level after mappings onto LUT-FPGAs.