Integrating Static Checking and Interactive Verification: Supporting Multiple Theories and Provers in Verification

Authors:
Joseph R. Kiniry;Patrice Chalin;Clément Hurlin
Affiliations:
Systems Research Group, School of Computer Science and Informatics, UCD Dublin, Belfield, Dublin, Ireland 4;Dependable Software Research Group Department of Computer Science and Software Engineering, Concordia University, Montreal, Canada H3G 1M8;Université Henri Poincaré, Nancy 1, Nancy Cedex, France
Venue:
Verified Software: Theories, Tools, Experiments
Year:
2005

Citing 9
Cited 0

Extended static checking for Java

PLDI '02 Proceedings of the ACM SIGPLAN 2002 Conference on Programming language design and implementation
Java Card Technology for Smart Cards: Architecture and Programmer's Guide

Java Card Technology for Smart Cards: Architecture and Programmer's Guide
The Java Language Specification

The Java Language Specification
JavaCard Program Verification

TPHOLs '01 Proceedings of the 14th International Conference on Theorem Proving in Higher Order Logics
Maude as a Formal Meta-tool

FM '99 Proceedings of the Wold Congress on Formal Methods in the Development of Computing Systems-Volume II
Simplify: a theorem prover for program checking

Journal of the ACM (JACM)
An overview of JML tools and applications

International Journal on Software Tools for Technology Transfer (STTT) - Special section on formal methods for industrial critical systems
Improving the Quality of Web-based Enterprise Applications with Extended Static Checking: A Case Study

Electronic Notes in Theoretical Computer Science (ENTCS)
ESC/Java2: uniting ESC/Java and JML

CASSIS'04 Proceedings of the 2004 international conference on Construction and Analysis of Safe, Secure, and Interoperable Smart Devices

Quantified Score

Hi-index	0.00

Visualization

Abstract

Automatic verification by means of extended static checking (ESC) has seen some success in industry and academia due to its lightweight and easy-to-use nature. Unfortunately, ESC comes at a cost: a host of logical and practical completeness and soundness issues. Interactive verification technology, on the other hand, is usually complete and sound, but requires a large amount of mathematical and practical expertise. Most programmers can be expected to use automatic, but not interactive, verification. The focus of this proposal is to integrate these two approaches into a single theoretical and practical framework, leveraging the benefits of each approach.