Partitioning Problems in Parallel, Pipeline, and Distributed Computing
IEEE Transactions on Computers
Optimal mapping of sequences of data parallel tasks
PPOPP '95 Proceedings of the fifth ACM SIGPLAN symposium on Principles and practice of parallel programming
Optimal latency-throughput tradeoffs for data parallel pipelines
Proceedings of the eighth annual ACM symposium on Parallel algorithms and architectures
Scheduling and Load Balancing in Parallel and Distributed Systems
Scheduling and Load Balancing in Parallel and Distributed Systems
Patterns and skeletons for parallel and distributed computing
Patterns and skeletons for parallel and distributed computing
Efficient collective communication in distributed heterogeneous systems
Journal of Parallel and Distributed Computing
Fast optimal load balancing algorithms for 1D partitioning
Journal of Parallel and Distributed Computing
BSP Functional Programming: Examples of a Cost Based Methodology
ICCS '08 Proceedings of the 8th international conference on Computational Science, Part I
Optimizing distributed computing workflows in heterogeneous network environments
ICDCN'10 Proceedings of the 11th international conference on Distributed computing and networking
High-level support for pipeline parallelism on many-core architectures
Euro-Par'12 Proceedings of the 18th international conference on Parallel Processing
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Mapping applications onto parallel platforms is a challenging problem, that becomes even more difficult when platforms are heterogeneous ---nowadays a standard assumption. A high-level approach to parallel programming not only eases the application developer's task, but it also provides additional information which can help realize an efficient mapping of the application. In this paper, we discuss the mapping of pipeline skeletons onto different types of platforms (from fully homogeneous to heterogeneous). We assume that a pipeline stage must be mapped on a single processor, and we establish new theoretical complexity results for two different mapping policies: a mapping can be either one-to-one (at most one stage per processor), or interval-based (interval of consecutive stages per processor). We provide several efficient polynomial heuristics for the most important policy/platform combination, namely interval-based mappings on platforms with identical communication links but different speed processors.