A fault analysis method for synchronous sequential circuits

Authors:
T. Y. Kuo;J. Y. Lee;J. F. Wang
Affiliations:
Institute of Electrical and Computer Engineering, National Cheng Kung University, Tainan, Taiwan, ROC;Institute of Electrical and Computer Engineering, National Cheng Kung University, Tainan, Taiwan, ROC;Institute of Electrical and Computer Engineering, National Cheng Kung University, Tainan, Taiwan, ROC
Venue:
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Year:
1991

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Cited 1

Multiple fault diagnosis in sequential circuits using sensitizing sequence pairs

FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)

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Abstract

In this paper we extend the use of the fault analysis method dealing with combinational circuits[1] to synchronous sequential circuits. Using the iterative array model, extended forward propagation and backward implication are performed. based on the observed values at primary outputs, to deduce the actual values of each line to determine its fault status. Any stuck fault can be identified, even in a circuit without any initialization sequence. A fault which is covered is tested unconditionally; thus the results obtained would not be invalidated in the presence of untested or untestable lines. Examples will be given to demonstrate the ability of our method.