A Low-Power 512-Bit EEPROM Design for UHF RFID Tag Chips

  • Authors:

  • Jae-Hyung Lee;Gyu-Ho Lim;Ji-Hong Kim;Mu-Hun Park;Kyo-Hong Jin;Jeong-Won Cha;Pan-Bong Ha;Yung-Jin Gang;Young-Hee Kim

  • Affiliations:

  • Changwon National University, 9 Sarim-dong, Changwon, Gyeongnam, 641-773, Korea;Changwon National University, 9 Sarim-dong, Changwon, Gyeongnam, 641-773, Korea;Changwon National University, 9 Sarim-dong, Changwon, Gyeongnam, 641-773, Korea;Changwon National University, 9 Sarim-dong, Changwon, Gyeongnam, 641-773, Korea;Changwon National University, 9 Sarim-dong, Changwon, Gyeongnam, 641-773, Korea;Changwon National University, 9 Sarim-dong, Changwon, Gyeongnam, 641-773, Korea;Changwon National University, 9 Sarim-dong, Changwon, Gyeongnam, 641-773, Korea;DavitDyne Co., Ltd., B 901-3, Ssangyoung IT Twin Tower, Sangdaewon-dong, Sungnam, Kyungki, 462-723, Korea;Changwon National University, 9 Sarim-dong, Changwon, Gyeongnam, 641-773, Korea

  • Venue:
  • ICCS '07 Proceedings of the 7th international conference on Computational Science, Part IV: ICCS 2007
  • Year:
  • 2007

Quantified Score

Hi-index 0.00

Visualization

Abstract

In this paper, a design for a low-power 512-bit synchronous EEPROM with flash cells for passive UHF RFID tag chip is presented. Applied are low-power schemes such as dual power supply voltage(VDD=1.5V and VDDP=2.5V), clocked inverter sensing, voltage-up converter, IO interface, and Dickson charge pump using schottky diode. An EEPROM is fabricated with the 0.25μm- EEPROM process. Simulation results show that power dissipations are 8.34μW in the read cycle and 57.7μW in the write cycle, respectively. The layout size is 449.3μm × 480.67μm.