Releasing and Scheduling of Lots in a Wafer Fab

  • Authors:

  • Subhash C. Sarin;Vinod D. Shenai;Lixin Wang

  • Affiliations:

  • Grado Department of Industrial and Systems Engineering, Virginia Tech, Blacksburg, VA 24061,;Grado Department of Industrial and Systems Engineering, Virginia Tech, Blacksburg, VA 24061,;Grado Department of Industrial and Systems Engineering, Virginia Tech, Blacksburg, VA 24061,

  • Venue:
  • AAIM '07 Proceedings of the 3rd international conference on Algorithmic Aspects in Information and Management
  • Year:
  • 2007

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Abstract

In this paper, we address the problem of both releasing and scheduling of lots in a wafer fab. In the lot release problem, we determine the number of lots of different products to be released in each period of a planning horizon in order to minimize total tardiness. The problem of the scheduling of lots at various workstations is modeled as a mathematical program for the objective of minimizing the cycle times of the lots and is solved by the Lagrangian relaxation method. Computational results are presented that exhibit that our methodology constantly generates better solutions compared to those obtained by commonly-used dispatching rules.