Design and Implementation of Rough Rules Generation from Logical Rules on FPGA Board

Authors:
Akinori Kanasugi;Mitsuhiro Matsumoto
Affiliations:
Department of Electronics, Tokyo Denki University, 2-2, Nishikicho, Chiyoda-ku, Tokyo 101-8457, Japan;Department of Electronics, Tokyo Denki University, 2-2, Nishikicho, Chiyoda-ku, Tokyo 101-8457, Japan
Venue:
RSEISP '07 Proceedings of the international conference on Rough Sets and Intelligent Systems Paradigms
Year:
2007

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Abstract

In this paper, the design, simulation, implementation and experiment of rough set processor are described. The experiment result shows that the proposed processor is ten times faster than PC, though the clock frequency is about 70 times lower.