FPGA-Based Real-Time Super-Resolution on an Adaptive Image Sensor

  • Authors:
  • Maria E. Angelopoulou;Christos-Savvas Bouganis;Peter Y. Cheung;George A. Constantinides

  • Affiliations:
  • Department of Electrical and Electronic Engineering, Imperial College London, London, UK SW7 2BT;Department of Electrical and Electronic Engineering, Imperial College London, London, UK SW7 2BT;Department of Electrical and Electronic Engineering, Imperial College London, London, UK SW7 2BT;Department of Electrical and Electronic Engineering, Imperial College London, London, UK SW7 2BT

  • Venue:
  • ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
  • Year:
  • 2008

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Abstract

Recent technological advances in imaging industry have lead to the production of imaging systems with high density pixel sensors. However, their long exposure times limit their applications to static images due to the motion blur effect. This work presents a system that reduces the motion blurring using a time-variant image sensor. This sensor can combine several pixels together to form a larger pixel when it is necessary. Larger pixels require shorter exposure times and produce high frame-rate samples with reduced motion blur. An FPGA is employed to enhance the spatial resolution of these samples employing Super Resolution (SR) techniques in real-time. This work focuses on the spatial resolution enhancement block and presents an FPGA implementation of the Iterative Back Projection (IBP) SR algorithm. The proposed architecture achieves 25 fps for VGA input and can serve as a general purpose real-time resolution enhancement system.