Analog CMOS Circuits Implementing Neural Segmentation Model Based on Symmetric STDP Learning

Authors:
Gessyca Maria Tovar;Eric Shun Fukuda;Tetsuya Asai;Tetsuya Hirose;Yoshihito Amemiya
Affiliations:
Hokkaido University, Sapporo, Japan 060-0814;Tokyo University, Chiba, Japan 277-8561;Hokkaido University, Sapporo, Japan 060-0814;Hokkaido University, Sapporo, Japan 060-0814;Hokkaido University, Sapporo, Japan 060-0814
Venue:
Neural Information Processing
Year:
2008

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Abstract

We proposed a neural segmentation model that is suitable for implementation in analog VLSIs using conventional CMOS technology. The model consists of neural oscillators mutually couple through synaptic connections. The model performs segmentation in temporal domain, which is equivalent to segmentation according to the spike timing difference of each neuron. Thus, the learning is governed by symmetric spike-timing dependent plasticity (STDP). We numerically demonstrate basic operations of the proposed model as well as fundamental circuit operations using a simulation program with integrated circuit emphasis (SPICE).