On Limits and Possibilities of Automated Protocol Analysis
Proceedings of the IFIP WG6.1 Seventh International Conference on Protocol Specification, Testing and Verification VII
Logic Verification of ANSI-C Code with SPIN
Proceedings of the 7th International SPIN Workshop on SPIN Model Checking and Software Verification
Verifying Time Partitioning in the DEOS Scheduling Kernel
Formal Methods in System Design
Parallel Randomized State-Space Search
ICSE '07 Proceedings of the 29th international conference on Software Engineering
The Design of a Multicore Extension of the SPIN Model Checker
IEEE Transactions on Software Engineering
Proceedings of the 2008 ACM SIGPLAN conference on Programming language design and implementation
Tool Presentation: Teaching Concurrency and Model Checking
Proceedings of the 16th International SPIN Workshop on Model Checking Software
EMMA: Explicit Model Checking Manager (Tool Presentation)
Proceedings of the 16th International SPIN Workshop on Model Checking Software
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Distributed and predictable software model checking
VMCAI'11 Proceedings of the 12th international conference on Verification, model checking, and abstract interpretation
Parallel symbolic execution for automated real-world software testing
Proceedings of the sixth conference on Computer systems
Towards informed swarm verification
NFM'11 Proceedings of the Third international conference on NASA Formal methods
Randomized backtracking in state space traversal
Proceedings of the 18th international SPIN conference on Model checking software
Multi-core nested depth-first search
ATVA'11 Proceedings of the 9th international conference on Automated technology for verification and analysis
(Quickly) testing the tester via path coverage
WODA '09 Proceedings of the Seventh International Workshop on Dynamic Analysis
SPIN'12 Proceedings of the 19th international conference on Model Checking Software
Parallel model checking using abstraction
SPIN'12 Proceedings of the 19th international conference on Model Checking Software
Conditional model checking: a technique to pass information between verifiers
Proceedings of the ACM SIGSOFT 20th International Symposium on the Foundations of Software Engineering
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The range of verification problems that can be solved with logic model checking tools has increased significantly in the last few decades. This increase in capability is based on algorithmic advances, but in no small measure it is also made possible by increases in processing speed and main memory sizes on standard desktop systems. For the time being, though, the increase in CPU speeds has mostly ended as chip-makers are redirecting their efforts to the development of multi-core systems. In the coming years we can expect systems with very large memory sizes, and increasing numbers of CPU cores, but with each core running at a relatively low speed. We will discuss the implications of this important trend, and describe how we can leverage these developments with new tools.