Amortized efficiency of list update and paging rules
Communications of the ACM
High-speed switch scheduling for local-area networks
ACM Transactions on Computer Systems (TOCS)
Wide area traffic: the failure of Poisson modeling
IEEE/ACM Transactions on Networking (TON)
Scheduling algorithms for input-queued cell switches
Scheduling algorithms for input-queued cell switches
The performance of simple routing algorithms that drop packets
Proceedings of the ninth annual ACM symposium on Parallel algorithms and architectures
Online computation and competitive analysis
Online computation and competitive analysis
Bounded latency scheduling scheme for ATM cells
Computer Networks: The International Journal of Computer and Telecommunications Networking
Competitve buffer management for shared-memory switches
Proceedings of the thirteenth annual ACM symposium on Parallel algorithms and architectures
Dynamic routing on networks with fixed-size buffers
SODA '03 Proceedings of the fourteenth annual ACM-SIAM symposium on Discrete algorithms
The zero-one principle for switching networks
STOC '04 Proceedings of the thirty-sixth annual ACM symposium on Theory of computing
Harmonic buffer management policy for shared memory switches
Theoretical Computer Science - Special issue: Online algorithms in memoriam, Steve Seiden
On the Performance of Greedy Algorithms in Packet Buffering
SIAM Journal on Computing
Scheduling policies for CIOQ switches
Journal of Algorithms
An improved algorithm for CIOQ switches
ACM Transactions on Algorithms (TALG)
Maximizing throughput in multi-queue switches
Algorithmica
An experimental study of new and known online packet buffering algorithms
ESA'07 Proceedings of the 15th annual European conference on Algorithms
FIFO queueing policies for packets with heterogeneous processing
MedAlg'12 Proceedings of the First Mediterranean conference on Design and Analysis of Algorithms
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Combined input and output queued (CIOQ) architectures with a moderate fabric speedupS 1 have come to play a major role in the design of high performance switches. In this paper we study CIOQ switches with First-In-First-Out (FIFO) buffers providing Quality of Service (QoS) guarantees. The goal of the switch policy is to maximize the total value of packets sent out of the switch. We analyze the performance of a switch policy by means of competitive analysis, where a uniform performance guarantee is provided for all traffic patterns. Azar and Richter [8] proposed an algorithm β-PG(Preemptive Greedy with a preemption factor of β) that is 8-competitive for an arbitrary speedup value when β= 3. We improve upon their result by showing that this algorithm achieves a competitive ratio of 7.5 and 7.47 for β= 3 and β= 2.8, respectively. Basically, we demonstrate that β-PGis at most $\frac{\beta^2 + 2\beta}{\beta - 1}$ and at least $\frac{\beta^2 - \beta + 1}{\beta - 1}$-competitive.