Formal Verification by Reverse Synthesis

  • Authors:

  • Xiang Yin;John C. Knight;Elisabeth A. Nguyen;Westley Weimer

  • Affiliations:

  • Department of Computer Science, Charlottesville, University of Virginia, Virginia, U.S.A.;Department of Computer Science, Charlottesville, University of Virginia, Virginia, U.S.A.;Software Systems Engineering Department, Chantilly, The Aerospace Corporation, Virginia, U.S.A.;Department of Computer Science, Charlottesville, University of Virginia, Virginia, U.S.A.

  • Venue:
  • SAFECOMP '08 Proceedings of the 27th international conference on Computer Safety, Reliability, and Security
  • Year:
  • 2008

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Abstract

In this paper we describe a novel yet practical approach to the formal verification of implementations. Our approach splits verification into two major parts. The first part verifies an implementation against a low-level specification written using source-code annotations. The second extracts a high-level specification from the implementation with the low-level specification, and proves that it implies the original system specification from which the system was built. Semantics-preserving refactorings are applied to the implementation in both parts to reduce the complexity of the verification. Much of the approach is automated. It reduces the verification burden by distributing it over separate tools and techniques, and it addresses both functional correctness and high-level properties at separate levels. As an illustration, we give a detailed example by verifying an optimized implementation of the Advanced Encryption Standard (AES) against its official specification.