An Architecture for Congestion Management in Ethernet Clusters
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 9 - Volume 10
An Architecture for Software-Based iSCSI on Multiprocessor Servers
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 9 - Volume 10
Exploiting NIC architectural support for enhancing IP-based protocols on high-performance networks
Journal of Parallel and Distributed Computing - Special issue: Design and performance of networks for super-, cluster-, and grid-computing: Part II
Efficient remote block-level I/O over an RDMA-capable NIC
Proceedings of the 20th annual international conference on Supercomputing
High performance and scalable I/O virtualization via self-virtualized devices
Proceedings of the 16th international symposium on High performance distributed computing
Frame shared memory: line-rate networking on commodity hardware
Proceedings of the 3rd ACM/IEEE Symposium on Architecture for networking and communications systems
FastForward for efficient pipeline parallelism: a cache-optimized concurrent lock-free queue
Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming
Practice of parallelizing network applications on multi-core architectures
Proceedings of the 23rd international conference on Supercomputing
SpringSim '09 Proceedings of the 2009 Spring Simulation Multiconference
An architecture for software-based iSCSI: experiences and analyses
NETWORKING'05 Proceedings of the 4th IFIP-TC6 international conference on Networking Technologies, Services, and Protocols; Performance of Computer and Communication Networks; Mobile and Wireless Communication Systems
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As part of an effort to accelerate server TCP/IP networking, Intel R&D has developed a software prototype that uses one of the intel xeon processors in a multiprocessor server as a packet processing engine (PPE). This prototype serves as a vehicle for empirical measurement and analysis of a highly programmable PPE that is closely tied to the server's core CPU and memory complex.