Power- and Complexity-Aware Issue Queue Designs

Authors:
Jaume Abella;Ramon Canal;Antonio Gonzalez
Affiliations:
Universitat Politècnica de Catalunya;Universitat Politècnica de Catalunya;Universitat Politècnica de Catalunya and Intel Barcelona Research Center
Venue:
IEEE Micro
Year:
2003

Citing 0
Cited 3

HeDGE: Hybrid Dataflow Graph Execution in the Issue Logic

HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
Folding active list for high performance and low power

ISHPC'05/ALPS'06 Proceedings of the 6th international symposium on high-performance computing and 1st international conference on Advanced low power systems
AVF-driven parity optimization for MBU protection of in-core memory arrays

Proceedings of the Conference on Design, Automation and Test in Europe

Quantified Score

Hi-index	0.00

Visualization

Abstract

The improved performance of current microprocessors brings with it increasingly complex and power-dissipating issue logic. Recent proposals introduce a range of mechanisms for tackling this problem.