Towards Automated FSMD Partitioning for Low Power Using Simulated Annealing
SAMOS '09 Proceedings of the 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
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It is well known that significant power savings can be obtained by disabling or shutting down parts of a circuit during idle periods. One method is to use a high level partitioning technique which considers both the controller and the datapath together. The FSMD is split into two or more simpler communicating processors. These separate processors can then be clock gated or power gated to achieve dramatic power savings since only one processor is active at any given time. Here, we propose a technique to efficiently partition a FSMD for power gating using an Integer Linear Programming (ILP) approach. Implementing and analyzing a sample circuit shows that up to 41% static and dynamic power savings are possible. We then develop a framework to estimate the potential power savings. Using several sample circuits, the estimation framework shows that up to 69% static power savings and 30% dynamic power savings can be expected.