A Digital Real Time Image Demosaicking Implementation for High Definition Video Cameras

  • Authors:

  • Jair Garcia-Lamont;Miguel Aleman-Arce;Julio Waissman-Vilanova

  • Affiliations:

  • -;-;-

  • Venue:
  • CERMA '08 Proceedings of the 2008 Electronics, Robotics and Automotive Mechanics Conference
  • Year:
  • 2008

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Abstract

This paper describes a digital real time image demosacking implementation for high definition video cameras. It comprises one buffer for three pixel rows and one interpolator based on bilinear interpolation. It has been implemented with HDL-Verilog and mapped onto Virtex-4 XC4VLX25 from Xilinx; for a clock frequency of 150MHZ, its throughput is 72 frames per second. This implementation may be used as an intellectual property for FPGA's or SoC.