Development of a Testbench for Validation of DMT and DT2 Fault-Tolerant Architectures on SOI PowerPC7448

Authors:
Michel Pignol;Thierry Parrain;Vincent Claverie;Christian Boléat;Guy Estaves
Affiliations:
-;-;-;-;-
Venue:
IOLTS '08 Proceedings of the 2008 14th IEEE International On-Line Testing Symposium
Year:
2008

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Abstract

The purpose of TAFT fault tolerance studies conducted at CNES is to prepare the space community for the significant evolution linked to the usage of COTS components for developing spacecraft supercomputers. CNES has patented the DMT and DT2 fault-tolerant architectures with 'light' features. The development of a DMT/DT2 testbench based on a PowerPC7448 microprocessor from e2v is presented in this paper.