Verification and implementation of software for dependable controllers
International Journal of Critical Computer-Based Systems
Formal modeling and synthesis of programmable logic controllers
Computers in Industry
Formal component-based modeling and synthesis for PLC systems
Computers in Industry
Hi-index | 0.01 |
A method is described for modeling, verification and automatic generation of code for PLC controllers. The modeling of requirements and the implementation of code are based on a definition of a finite state time machine. The verification process uses UPPAAL, a model checking tool for the networks of timed automata. A conversion between both models is done automatically. The method starts from modeling the desired behavior of the controller by means of an UML-based state machine diagram, and ends-up with a complete program in one of the IEC 1131 languages.