Reconfigurable Operator Based Multimedia Embedded Processor
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
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This paper presents the exploration and design of a high-efficiency processor element for multimedia application. Based on the cost estimation model to evaluate the area and energy consumption for synchronous data transport architecture, a divide and-conquer design approach is proposed to generate the optimal processor element in a short time. The computing core exploration begins with the application characteristics analysis, and continues with a heuristic search process for the performance energy Pareto optimal cores. Then, the trace-driven simulation and analytical method explore the processor elements which are optimal with respect to performance-energy under area constraint. The automated design approach generates the target processor element within 4 hours, and the processor implemented in UMC 0.13um CMOS process can operate at 500MHz while consuming average 223mW power. For multimedia applications, the generated processor has the comparable performance with the state-of-art high performance DSPs.