POD: A 3D-Integrated Broad-Purpose Acceleration Layer

Authors:
Dong Hyuk Woo;Hsien-Hsin S. Lee;Joshua B. Fryman;Allan D. Knies;Marsha Eng
Affiliations:
Georgia Institute of Technology;Georgia Institute of Technology;Intel;Intel;Intel
Venue:
IEEE Micro
Year:
2008

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Abstract

To build a future many-core processor, industry must address the challenges of energy consumption and performance scalability. A 3D-integrated broad-purpose accelerator architecture called parallel-on-demand (POD) integrates a specialized SIMD-based die layer on top of a CISC superscalar processor to accelerate a variety of data-parallel applications. It also maintains binary compatibility and facilitates extensibility by virtualizing the acceleration capability.