Interconnection networks for large-scale parallel processing: theory and case studies
Interconnection networks for large-scale parallel processing: theory and case studies
Fault location techniques for distributed control interconnection networks
IEEE Transactions on Computers
Shared memory parallel processors: the butterfly and the monarch
Proceedings of the fourth MIT conference on Advanced research in VLSI
Polynomial Testing of Packet Switching Networks
IEEE Transactions on Computers
Concurrent error detection in VLSI interconnection networks
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Banyan networks for partitioning multiprocessor systems
ISCA '73 Proceedings of the 1st annual symposium on Computer architecture
Built-in self test architectures for multistage interconnection networks
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Performance analysis and fault tolerance of randomized routing on Clos networks
FRONTIERS '96 Proceedings of the 6th Symposium on the Frontiers of Massively Parallel Computation
Diagnosing crosstalk-faulty switches in photonic networks
SRDS '96 Proceedings of the 15th Symposium on Reliable Distributed Systems
Testing Layered Interconnection Networks
IEEE Transactions on Computers
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The authors present efficient methods for testing packet-switched multistage interconnection networks. In addition to testing the data paths and routing capabilities, tests for detecting faults in the control circuitry including the conflict resolution capabilities are provided. Using a general model of the switch, testing sequences are constructed for the internal functions of the f*f switch requiring only O(f/sup 2/2/sup f/) tests in the case of round-robin priority and O(f2/sup f-1/) in the case of fixed priority (f is usually a constant that is less than or equal to eight). Algorithms are then presented to test the entire network using at most twice the number of tests needed to test a switch, independently of the network size, which results in O(log N) testing time for an N-processor network. It is shown that the method achieves higher coverage and several-orders-of-magnitude reduction in the testing time of complex multiprocessor systems compared to previous methods.