System design with Ada
Programming in Prolog (2nd ed.)
Programming in Prolog (2nd ed.)
A 15 Year Perspective on Automatic Programming
IEEE Transactions on Software Engineering - Special issue on artificial intelligence and software engineering
Proving liveness for networks of communicating finite state machines
ACM Transactions on Programming Languages and Systems (TOPLAS) - The MIT Press scientific computation series
Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
IEEE Transactions on Software Engineering
IEEE Transactions on Software Engineering
Salient features of and executable specification language and its environment
IEEE Transactions on Software Engineering
Software CAD: A Revolutionary Approach
IEEE Transactions on Software Engineering
A general-purpose algorithm for analyzing concurrent programs
Communications of the ACM
Practical visual techniques in system design: with applications to Ada
Practical visual techniques in system design: with applications to Ada
Starvation and Critical Race Analyzers for Ada
IEEE Transactions on Software Engineering
Experience with the automatic temporal analysis of multitasking Ada designs
SIGAda '87 Proceedings of the 1987 annual ACM SIGAda international conference on Ada
A model and temporal proof system for networks of processes
POPL '85 Proceedings of the 12th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
On Communicating Finite-State Machines
Journal of the ACM (JACM)
An Introduction to Proving the Correctness of Programs
ACM Computing Surveys (CSUR)
ACM Computing Surveys (CSUR)
Proving Liveness Properties of Concurrent Programs
ACM Transactions on Programming Languages and Systems (TOPLAS)
Concurrent control with “readers” and “writers”
Communications of the ACM
Reference Manual for the ADA Programming Language
Reference Manual for the ADA Programming Language
A Calculus of Communicating Systems
A Calculus of Communicating Systems
Verifying Concurrent Processes Using Temporal Logic
Verifying Concurrent Processes Using Temporal Logic
Logic for Problem Solving
The temporal logic of branching time
POPL '81 Proceedings of the 8th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Verification of Concurrent Programs: Temporal Proof Principles
Logic of Programs, Workshop
Specification and Verification of Real-Time, Distributed Systems Using the Theory of Constraints
Proceedings of the 5th Conference on Automated Deduction
A Decision Method for Linear Temporal Logic
Proceedings of the 7th International Conference on Automated Deduction
Synthesis of communicating processes from temporal logic specifications
Synthesis of communicating processes from temporal logic specifications
Languages for representing software specifications and designs
ACM SIGSOFT Software Engineering Notes
Extending Statecharts with Temporal Logic
IEEE Transactions on Software Engineering
Comments on 'Temporal Logic-Based Deadlock Analysis for Ada' by G.M. Karam and R.J.A. Burh
IEEE Transactions on Software Engineering
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A temporal logic-based specification language and deadlock analyzer for Ada is described. The deadlock analyzer is intended for use within Timebench, a concurrent system-design environment with support for Ada. The specification language, COL, uses linear-time temporal logic to provide a formal basis for axiomatic reasoning. The deadlock analysis tool uses the reasoning power of COL to demonstrate that Ada designs specified in COL are systemwide deadlock-free: in essence, it uses a specialized theorem prover to deduce the absence of deadlock. The deadlock algorithm is shown to be decidable for finite systems and acceptable otherwise. It is also shown to have a worst-case computational complexity that is exponential with the number of tasks. The analyzer has been implemented in Prolog. Numerous examples are evaluated using the analyzer, including readers and writers, gas station, five dining philosophers, and a layered communications system. The results indicate that analysis time is reasonable for moderate designs in spite of the worst-case complexity of the algorithm .