Can parallel algorithms enhance serial implementation

• Authors: Uzi Vishkin
• Venue: ACM SIGACT News
• Year: 1991

Consider the serial emulation of a parallel algorithm. The thesis presented in this informal paper is rather broad. It suggests that such a serial emulation has the potential advantage of running on a serial machine faster than a standard serial algorithm for the same problem.The main concrete observation is very simple: just before the serial emulation of a round of the parallel algorithm begins, the whole list of memory addresses needed during this round is readily available; and, we can start fetching these addresses from secondary memories.This enables to prefetch the data that will be needed in the next "time window", perhaps by means of pipelining and have them ready at the fast memories when requested by the CPU. Thereby, utilization of commonly used memory management systems will be theoretically enhanced. Another (considerably less orthodox) implementation approach will result in abandoning locality of references, in favor of a drastically different approach: distribute memory addresses at random over memory modules, as has been proposed in the context of implementing the parallel-random-access machine (PRAM) design space.It is too early to reach conclusions regarding the significance of the thesis of this paper. Serious attempts to follow it up are needed to determine its usefulness. Parts of this paper are intentionally written in an informal way, suppressing issues that will have to be resolved in the context of a concrete implementation. My general intention is to encourage colleagues to: (i) suggest other specific approaches, and (ii) explore opportunities for taking advantage of the fine structure of parallel programs well beyond concrete suggestions made in the paper.The full paper is available as UMIACS TR 91-145, from the Institute for Advanced Computer Studies, University of Maryland, College Park, Maryland 20742--3251.