Leveraging on-chip networks for data cache migration in chip multiprocessors

  • Authors:

  • Noel Eisley;Li-Shiuan Peh;Li Shang

  • Affiliations:

  • Princeton University, Princeton, NJ, USA;Princeton University, Princeton, NJ, USA;University of Colorado - Boulder, Boulder, CO, USA

  • Venue:
  • Proceedings of the 17th international conference on Parallel architectures and compilation techniques
  • Year:
  • 2008

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Abstract

Recently, chip multiprocessors (CMPs) have arisen as the de facto design for modern high-performance processors, with increasing core counts. An important property of CMPs is that remote, but on-chip, L2 cache accesses are less costly than off-chip accesses; this is in contrast to earlier chip-to-chip or board-to-board multiprocessors, where an access to a remote node is just as costly if not more so than a main memory access. This motivates on-chip cache migration as a means to retain more data on-chip. However, previously proposed techniques do not scale to high core counts: they do not leverage the on-chip caches of all cores nor have a scalable migration mechanism. In this paper we propose ascalable in-network migration technique which uses hints embedded within the router microarchitecture to steer L2 cache evictions towards free/invalid cache slots in any on-chip core cache, rather than evicting it off-chip. We show that our technique can provide an average of a 19% reduction in the number of off-chip memory accesses over the state-of-the-art, beating the performance of a pseudo-optimal migration technique. This can be done with negligible area overhead and a manageable traffic overhead of 13.4%.