Optimal overlapped message passing decoding of quasi-cyclic LDPC codes

Authors:
Yongmei Dai;Zhiyuan Yan;Ning Chen
Affiliations:
Department of Electrical and Computer Engineering, Lehigh University, Bethlehem, PA;Department of Electrical and Computer Engineering, Lehigh University, Bethlehem, PA;Department of Electrical and Computer Engineering, Lehigh University, Bethlehem, PA
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2008

Citing 12
Cited 4

Error control systems for digital communication and storage

Error control systems for digital communication and storage
Low-power VLSI decoder architectures for LDPC codes

Proceedings of the 2002 international symposium on Low power electronics and design
Partially-Parallel LDPC Decoder Based on High-Efficiency Message-Passing Algorithm

ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Some Classes of Quasi-Cyclic LDPC Codes: Properties and Efficient Encoding Method*This paper was presented in part at the 26th Symposium on Information Theory and Its Applications, Higashiura, Hyogo, Japan, December 15--18, 2003 and at IEEE International Symposium on Information Theory, Chicago, IL USA, June 27--July 2, 2004.

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Partially-Parallel LDPC Decoder Achieving High-Efficiency Message-Passing Schedule

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
High-throughput LDPC decoders

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Joint (3,k)-regular LDPC code and decoder/encoder design

IEEE Transactions on Signal Processing
Factor graphs and the sum-product algorithm

IEEE Transactions on Information Theory
Low-density parity-check codes based on finite geometries: a rediscovery and new results

IEEE Transactions on Information Theory
Quasicyclic low-density parity-check codes from circulant permutation matrices

IEEE Transactions on Information Theory
LDPC block and convolutional codes based on circulant matrices

IEEE Transactions on Information Theory
Iterative decoder architectures

IEEE Communications Magazine

FPGA-based low-complexity high-throughput tri-mode decoder for quasi-cyclic LDPC codes

Allerton'09 Proceedings of the 47th annual Allerton conference on Communication, control, and computing
Spectral graph analysis of quasi-cyclic codes

GLOBECOM'09 Proceedings of the 28th IEEE conference on Global telecommunications
Accelerating FPGA-based emulation of quasi-cyclic LDPC codes with vector processing

Proceedings of the Conference on Design, Automation and Test in Europe
QSN: a simple circular-shift network for reconfigurable quasi-cyclic LDPC decoders

IEEE Transactions on Circuits and Systems II: Express Briefs

Quantified Score

Hi-index	0.00

Visualization

Abstract

Efficient hardware implementation of low-density parity-check (LDPC) codes is of great interest since LDPC codes are being considered for a wide range of applications. Recently, overlapped message passing (OMP) decoding has been proposed to improve the throughput and hardware utilization efficiency (HUE) of decoder architectures for LDPC codes. In this paper, we first study the scheduling for the OMP decoding of LDPC codes, and show that maximizing the throughput gain amounts to minimizing the intra- and inter-iteration waiting times. We then focus on the OMP decoding of quasi-cyclic (QC) LDPC codes. We propose a partly parallel OMP decoder architecture and implement it using FPGA. For any QC LDPC code, our OMP decoder achieves the maximum throughput gain and HUE due to overlapping, hence has higher throughput and HUE than previously proposed OMP decoders while maintaining the same hardware requirements. We also show that the maximum throughput gain and HUE achieved by our OMP decoder are ultimately determined by the given code. Thus, we propose a coset-based construction method, which results in QC LDPC codes that allow our optimal OMP decoder to achieve higher throughput and HUE.