Soft-error resilience of the IBM POWER6 processor

Authors:
P. N. Sanda;J. W. Kellington;P. Kudva;R. Kalla;R. B. McBeth;J. Ackaret;R. Lockwood;J. Schumann;C. R. Jones
Affiliations:
IBM Systems and Technology Group, Poughkeepsie, New York;IBM Systems and Technology Group, Austin, Texas;IBM Research Division, Thomas J. Watson Research Center, Yorktown Heights, New York;IBM Systems and Technology Group, Austin, Texas;IBM Systems and Technology Group, Austin, Texas;IBM Systems and Technology Group, Beaverston, Oregon;IBM Systems and Technology Group, Essex Junction, Vermont;IBM Systems and Technology Group, Austin, Texas;IBM Systems and Technology Group, Austin, Texas
Venue:
IBM Journal of Research and Development
Year:
2008

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Abstract

The error detection and correction capability of the IBM POWER6™ processor enables high tolerance to single-event upsets. The soft-error resilience was tested with proton beam- and neutron beam-induced fault injection. Additionally, statistical fault injection was performed on a hardware-emulated POWER6 processor simulation model. The error resiliency is described in terms of the proportion of latch upset events that result in vanished errors, corrected errors, checkstops, and incorrect architected states.