A PLL-based synthesizer for tunable digital clock generation in a continuous-time ΣΔ A/D converter

  • Authors:

  • Jokin Segundo;Luis Quintanilla;Jesús Arias;Lourdes Enríquez;Jesús M. Hernández;José Vicente

  • Affiliations:

  • Departamento de Electricidad y Electrónica, E.T.S.I. de Telecomunicación, Campus Miguel Delibes, Universidad de Valladolid, 47011 Valladolid, Spain;Departamento de Electricidad y Electrónica, E.T.S.I. de Telecomunicación, Campus Miguel Delibes, Universidad de Valladolid, 47011 Valladolid, Spain;Departamento de Electricidad y Electrónica, E.T.S.I. de Telecomunicación, Campus Miguel Delibes, Universidad de Valladolid, 47011 Valladolid, Spain;Departamento de Electricidad y Electrónica, E.T.S.I. de Telecomunicación, Campus Miguel Delibes, Universidad de Valladolid, 47011 Valladolid, Spain;Departamento de Electricidad y Electrónica, E.T.S.I. de Telecomunicación, Campus Miguel Delibes, Universidad de Valladolid, 47011 Valladolid, Spain;Departamento de Electricidad y Electrónica, E.T.S.I. de Telecomunicación, Campus Miguel Delibes, Universidad de Valladolid, 47011 Valladolid, Spain

  • Venue:
  • Integration, the VLSI Journal
  • Year:
  • 2009

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Abstract

In this paper, the design and implementation of a tunable clock synthesizer for driving two continuous-time @S@D ADCs has been carried out. A PLL-based solution, whose phase noise requirements are obtained from system level simulations, was implemented in a 0.35@mm CMOS technology. The frequency of the clock ranges from 12 to 256MHz with a minimum tuning step of 10kHz. The PLL phase noise is kept below -80dBc/Hz at 1MHz offset for the entire output range, while drawing 2.2-5.6mA from a 3.3V supply voltage.